In the manufacturing of semiconductor devices, fine processing is nowadays approaching physical limits. In order to compensate for such limits, it has been proposed to enhance integration of semiconductor devices by stacking structural elements in height directions. This integration tendency is particularly notable in NAND flash memories. The research and development of three-dimensional NAND flash memories are being actively pursued.
For Example, Non-Patent Document 1 discloses a three-dimensional NAND flash memory which includes: a laminated film having a plurality of layers of polycrystalline silicon (hereinafter referred to as “poly-Si” or “p-Si”) and layers of silicon oxide (hereinafter referred to as “SiOx”) alternately laminated together on a substrate; and structural elements as electrodes embedded in the laminated film vertically to the layers. In the actual manufacturing of this memory device, however, damage is caused to the substrate during etching of the laminated film because both of the underlying substrate and the respective layers of the laminated film are made of Si materials. It is difficult to etch only the laminated film of p-Si and SiOx.
Hence, Non-Patent Document 2 proposes an NAND flash memory using a laminated film of silicon nitride (hereinafter referred to as “SiN”) and SiOx in place of a laminated film of p-Si and SiOx. In one example of manufacturing method of this memory device, an alternate laminated film of SiN layers 1 and SiOx, layers 2 is provided on a substrate 4 as shown in FIG. 1(a) and then subjected to etching to form through holes 5 vertically to the layers as shown in FIG. 1(b). After that, gates are formed by removing the SiN layers although not specifically shown in the figures.
As a method for formation of the through hole in the direction vertical to the layers of the laminated film, Non-Patent Document 3 discloses formation of a through hole in an alternate laminated film of Si and SiO2 by alternately and independently repeating etching of Si and etching of SiO2 during manufacturing of a mass memory called BiCS.
When etching steps are independently performed on the respective layers, however, the number of etching steps significantly increases with increase in the number of layers laminated. When only a conventional CF-based gas is used, the etching rate of SiN is low; and, in some cases, deposition occurs on the SiN layers so that it is not possible to obtain a desired etching shape. Patent Document 1 hence proposes a method for simultaneously etching different kinds of layers in one plasma etching step with the use of a mixed gas containing a CF-based gas and a CHF-based gas.
Furthermore, Patent Document 2 discloses an etching agent containing a fluorine-containing unsaturated hydrocarbon such as HFO-1234ze(E). This etching agent allows high aspect ratio etching because of high etching rate for both SiN and SiO2 and high selectivity to mask material.